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Si552
Table 3. CLK± Output Frequency Characteristics
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Nominal Frequency
1,2,3
f O
LVDS/CML/LVPECL
10
—
945
MHz
CMOS
10
—
160
MHz
Temperature Stability
1,4
T A = –40 to +85 °C
–20
–50
–100
—
—
—
+20
+50
+100
ppm
Absolute Pull Range 1,4
Aging
Power up Time 5
Settling Time After FS Change
APR
t OSC
t FRQ
Frequency drift over first year.
Frequency drift over 15 year life.
±12
—
—
—
—
—
—
—
—
—
±375
±3
±10
10
10
ppm
ppm
ppm
ms
ms
Notes:
1. See Section 3. "Ordering Information" on page 10 for further details.
2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.
3. Nominal output frequency set by V CNOM = V DD /2.
4. Selectable parameter specified by part number.
5. Time from power up or tristate mode to f O (to within ±1 ppm of f O ).
Table 4. CLK± Output Levels and Symmetry
Parameter
LVPECL Output
Option 1
Symbol
V O
V OD
V SE
Test Condition
mid-level
swing (diff)
swing (single-ended)
Min
V DD – 1.42
1.1
0.55
Typ
—
—
—
Max
V DD – 1.25
1.9
0.95
Units
V
V PP
V PP
LVDS Output Option
2
V O
V OD
mid-level
swing (diff)
1.125
0.5
1.20
0.7
1.275
0.9
V
V PP
CML Output Option 2
V O
V OD
2.5/3.3 V option mid-level
1.8 V option mid-level
2.5/3.3 V option swing (diff)
1.8 V option swing (diff)
—
—
1.10
0.35
V DD – 1.30
V DD – 0.36
1.50
0.425
—
—
1.90
0.50
V
V
V PP
V PP
CMOS Output
Option 3
V OH
V OL
I OH = 32 mA
I OL = 32 mA
0.8 x V DD
—
—
—
V DD
0.4
V
V
Rise/Fall time (20/80%)
t R, t F
LVPECL/LVDS/CML
CMOS with C L = 15 pF
—
—
—
1
350
—
ps
ns
Symmetry (duty cycle)
SYM
LVPECL:
V DD – 1.3 V (diff)
LVDS:
1.25 V (diff)
45
—
55
%
Notes:
1. 50 ? to V DD – 2.0 V.
2. R term = 100 ? (differential).
3. C L = 15 pF
CMOS:
V DD /2
Rev. 1.1
3
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